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Suitable for university projects up to high-volume applications
The GateMate™ FPGA family of Cologne Chip AG addresses all application requirements of small to medium size FPGAs. Logic capacity, power consumption, package size, and PCB compatibility are best in class. GateMate™ FPGAs combine these features with the lowest cost in the industry making the devices well-suited for University projects to high volume applications. Because of the outstanding circuit size/cost ratio, new applications now can use the benefits of FPGAs.
All this is based on a novel FPGA architecture combining CPE programmable elements with a smart routing engine. The CPE architecture allows an efficient building of arbitrarily-sized multipliers. Memory-aware applications can use block RAMs with bit widths of 1 to 80 bits.
General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volts. All GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore, a high-speed SerDes interface is available.
FPGA designs are synthesized using the Yosys framework. The free Cologne Chip P&R-software generates the FPGA bitstream. A Static Timing Analysis (STA) is also performed and gives evidence about critical paths and the overall performance of a design. The design can be simulated using Verilog netlist and SDF timing extraction.
The devices are manufactured using Globalfoundries™ 28 nm SLP (Super Low Power) process.
GateMate™ FPGA is designed and manufactured in Germany.